The process of designing integrated circuits typically involves a functional design step, followed by a physical design step. During the functional design step, a design concept is described using a hardware description language and is then converted into a netlist, which specifies the electronic components and the connections between the components. The physical design step specifies the placement of the electronic components or elements on the chip and routing of the connections between the electronic components, thereby implementing the netlist. The physical design process generates the physical design data, which are synonymously called layout data, layout, or target layout.
The layout data defines a set of binary patterns or objects, which are also called “geometric features” or “features”. Usually the objects are represented as a polygon or collection of polygons in the layout data in order to facilitate the specification of the objects.
Each object can be a part of an electronic component such as a gate of a transistor or a connection between components. Each polygon object has vertices and edges joining those vertices. Each vertex is usually defined by its coordinates in a Cartesian x-y coordinate system. In a typical very-large scale integrated (VLSI) circuit, most edges are parallel to the x or y axis, in a so-called Manhattan layout style.
Often the physical layout data are stored and transmitted in a machine-readable format such as GDSII format, OASIS™ format, or in a database such as OpenAccess database or Milkyway™ design database. See, for example, OpenAccess: The Standard API for Rapid EDA Tool Integration, ©2004 by Si2, Inc.; Milkyway Foundation Database for Nanometer Design, ©2003 by Synopsys, Inc.
In these formats or databases, the layouts are often described hierarchically. This has the advantage of reducing file sizes and improving efficiency for certain analysis or modification operations, since some repetitive patterns can be given certain unique names and then placed multiple times in the layout by simply referring to those names. Repeatedly describing or performing computations for the same structure in detail can thus be avoided.
In a hierarchical layout description, a cell is a collection of layout features that can be referenced as a whole object. Thus, cells can be included in the layout by reference. Inclusions by reference can further be nested.
Figuratively, the hierarchy of the layout resembles a tree. The leaves of a tree are attached to its branches. Branches are attached to larger branches. The hierarchy of branches continues until the trunk of the tree reaches its root. “Leaf cells” of a layout are cells that do not include any other cells by reference. A leaf cell comprises a set of primitive objects or features, which are usually polygons. A “child cell” is included in its “parent cell.” A “root cell” is not included in any other. A layout can have multiple root cells, resembling a forest with multiple trees. And cells can be referenced any number of times within a single parent cell or by multiple parent cells.
Cell references can take one of two forms: a Structure Reference (SREF) or an Array Reference (AREF). A structure reference places an instance (a copy) of a cell at a particular (x,y)-offset within a parent cell. Each instance has some transformation information, which can often include translation, magnification, reflection, and/or rotation. An array reference describes multiple instances of a cell that are placed on a set of locations that form a regular grid or array. The array is defined by: 1) a number of rows; 2) a number of columns, 3) row and column spacings, 4) (x, y) offset of an instance; and 5) a set of magnification, reflection, and rotation that are common to all cells in the array.
If a layout does not have hierarchy, it is called flat. A layout can be flat as per design. Sometimes a hierarchical layout can be flattened. “Flattening a layout” means removing its hierarchical organization by replacing each cell reference by the set of geometric features contained in the cell that is referenced.
Semiconductor device manufacturing comprises many steps of patterning layers of silicon wafers according to the layout data. A layer is either the substrate of the semiconductor wafer or a film deposited on the wafer. At some steps, a pattern is etched into a layer. At some other steps, ions are implanted, usually in a pattern, into the layer. Generally, patterning comprises: lithographic exposure, resist development, and resist etching.
The prevalent form of lithography is optical projection lithography. This involves first making a mask or reticle that embodies the pattern to be projected onto the wafer. An image of the mask's pattern is then optically projected onto a photoresist film coated on the wafer. This selectively exposes the photoresist. The latent image is then developed, thereby making a stencil on the wafer.
Presently, the most common optical lithography projectors are stepper-scanners. These instruments expose a slit shaped region, which is often 26 millimeters (mm)×8 mm on the wafer. The wafer is scanned under the slit by a motorized stage under interferometer control. The mask is scanned in synchronization with the wafer but at a higher speed to account for the reduction of the projector (typically 4×). One scan typically exposes a 26 mm×33 mm image field. Step-and-repeat lithography projectors expose the wafer a field at a time. A common field size here is 22 mm×22 mm. In either case, many exposure fields are needed to cover the wafer.
Other forms of lithography include mask-less optical projection lithography, where the mask is replaced by a spatial light modulator. The spatial modulator is typically an array of micro-machined mirrors that are illuminated and imaged onto the wafer. The spatial light modulator is driven by the lithography data. Direct electron-beam writing lithography, electron projection lithography, and imprint lithography are other forms of lithography.
Modern semiconductor lithography processes often print features that are smaller than the exposure wavelength. In this regime, called the low-k1 regime, the field and wave nature of light is prevalent, and the finite aperture of the projection lens acts as a low-pass filter of spatial frequencies in the image. Thus, it may be difficult for the projection lens to reproduce the high spatial frequency components required to reproduce the sharp edges or corners in polygon objects, for example. Also, light entering a mask opening from one object may impact another shape in close proximity, leading to a complex interaction of the electric fields of adjacent objects. Thus, the final shapes that are produced on the wafer will often have rounded corners and may bulge towards adjacent objects in ways that can impact the process yield. This resulting image distortion, called optical proximity effect, is responsible for the most significant distortion that arises in the transfer of the mask pattern onto the wafer.
Optical Proximity Correction (OPC) is the process of changing, or pre-distorting, the target layout data to produce the lithography or mask data so that the pattern that is etched in the wafer is a closer replica of the target layout. The goal of OPC is to counter the distortions caused by the physical patterning process (see A. K-T Wong, Resolution enhancement techniques in optical lithography, SPIE Press, Vol. TT47, Bellingham, Wash., 2001; H. J. Levinson, Principles of Lithography, SPIE Press, Bellingham, Wash., 2001). In effect, the objects or polygons of the lithography data are modifications from those specified by the target layout in an effort to improve the reproduction fidelity of the critical geometric features. This is often accomplished by moving object edges and by adding additional objects to the layout to counter optical and process distortions. These corrections are required to ensure the intended target design pattern fidelity is met, improving the process window and consequently manufacturing yield.
Application of many resolution enhancement technologies (RET) can also have the effect of changing the layout data relative to the lithography data. RET also addresses distortion in the lithography process by pre-compensation. Typically, RET involves implementing a resolution enhancement technique such as the insertion of sub-resolution assist features (SRAF), phase shift enhancement using an attenuated phase mask, or designing a mask that includes quartz etching to introduce phase shifting across features.
Still further, functional requirements can lead to changes when migrating from the layout data to the lithography data. For example, electronic elements, including conductive traces and transistors, that lie on critical paths may be more aggressively modified to improve yields, possibly at the expense of other, lower priority paths.
In short, the target layout describes the pattern that the designer desires to render on the wafer to form the integrated circuit. It is usually different than the pattern that is actually rendered on the integrated circuit, and is therefore usually very different than the pattern submitted to the mask making process due to implementations of RET and OPC. Thus, the target layout, the lithography or mask data, and the pattern resulting on the wafer are typically distinct patterns.
Different techniques are used to simulate the transformation between the mask pattern and the pattern that is formed in the photo resist. The process for generating the OPC, RET, and other compensations for a given object or mask is typically an iterative process involving moving parts of or adding to the objects, and determining if the new objects result in a better resist pattern. In model-based OPC or RET, various process effects are simulated. Model-based OPC, for example, is a numerically intensive calculation that transforms the target layout into mask data.